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K6F2016V4E Family
Document Title
CMOS SRAM
128K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
0.0 1.0 Initial Draft Finalize
Draft Date
November 27, 2001 March 8, 2002
Remark
Preliminary Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
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Revision 1.0 March 2002
K6F2016V4E Family
FEATURES
* * * * * *
CMOS SRAM
GENERAL DESCRIPTION
The K6F2016V4E families are fabricated by SAMSUNGs advanced full CMOS process technology. The families support industrial temperature range and 48 ball Chip Scale Package for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current.
128K x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Process Technology: Full CMOS Organization: 128K x16 bit Power Supply Voltage: 3.0~3.6V Low Data Retention Voltage: 1.5V(Min) Three State Outputs Package Type: 48-TBGA-6.00x7.00
PRODUCT FAMILY
Power Dissipation Product Family Operating Temperature Vcc Range Speed Standby (ISB1, Typ.) 0.5A2) Operating (ICC1, Max) 4mA PKG Type
K6F2016V4E-F
Industrial(-40~85C)
3.0~3.6V
551)/70ns
48-TBGA-6.00x7.00
1. The parameter is measured with 30pF test load. 2. Typical values are measured at VCC=3.3V, TA=25C and not 100% tested.
PIN DESCRIPTION
1 2 3 4 5 6
FUNCTIONAL BLOCK DIAGRAM
Clk gen. Precharge circuit.
A
LB
OE
A0
A1
A2
DNU Vcc Vss
B
I/O9
UB
A3
A4
CS1
I/O1
Row Addresses
C
I/O10
I/O11
A5
A6
I/O2
I/O3
Row select
Memory array 1024 rows 128 x 16 columns
D
Vss
I/O12
DNU
A7
I/O4
Vcc
E
Vcc
I/O13
DNU
A16
I/O5
Vss
I/O1~I/O8
Data cont Data cont Data cont
I/O Circuit Column select
F
I/O15
I/O14
A14
A15
I/O6
I/O7
I/O9~I/O16
G
I/O16
DNU
A12
A13
WE
I/O8 Column Addresses
H
DNU
A8
A9
A10
A11
DNU
48-TBGA: Top View (Ball Down) Name Function Name Vcc Vss UB LB DNU Function Power Ground Upper Byte(I/O9~16) Lower Byte(I/O1~8) Do Not Use
CS OE WE UB LB
Control Logic
CS1, CS2 Chip Select Inputs OE WE A0~A16 Output Enable Input Write Enable Input Address Inputs
I/O1~I/O16 Data Inputs/Outputs
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
-2Revision 1.0 March 2002
K6F2016V4E Family
PRODUCT LIST
Industrial Temperature Products(-40~85C) Part Name K6F2016V4E-EF55 K6F2016V4E-EF70 Function
CMOS SRAM
48-TBGA, 55ns, 3.3V 48-TBGA, 70ns, 3.3V
FUNCTIONAL DESCRIPTION
CS H X1) L L L L L L L L OE X
1)
WE X
1)
LB X
1)
UB X
1)
I/O1~8 High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din
I/O9~16 High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din
Mode Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
Power Standby Standby Active Active Active Active Active Active Active Active
X1) H H L L L X
1)
X1) H H H H H L L L
H L X1) L H L L H L
H X
1)
L H L L H L L
X1) X
1)
1. X means dont care.(Must be low or high state.)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN, VOUT VCC PD TSTG TA Ratings -0.2 to VCC+0.3V -0.2 to 4.0V 1.0 -65 to 150 -40 to 85 Unit V V W C C
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions longer than 1seconds may affect reliability.
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K6F2016V4E Family
RECOMMENDED DC OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input low voltage
Note: 1. TA=-40 to 85C, otherwise specified. 2. Overshoot: Vcc+2.0V in case of pulse width 20ns. 3. Undershoot: -2.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested.
CMOS SRAM
Symbol Vcc Vss VIH VIL
Min 3.0 0 2.2 -0.23)
Typ 3.3 0 -
Max 3.6 0 Vcc+0.2 0.6
2)
Unit V V V V
CAPACITANCE1) (f=1MHz, TA=25C)
Item Input capacitance Input/Output capacitance
1. Capacitance is sampled, not 100% tested.
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Symbol ILI ILO ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current (CMOS) VOL VOH ISB1 Cycle time=Min, IIO=0mA, 100% duty, CS=VIL, LB=VIL or/and UB=VIL, VIN=VIL or VIH IOL = 2.1mA IOH = -1.0mA Other input =0~Vcc 1) CSVcc-0.2V(CS controlled) or 2) LB=UBVcc-0.2V, CS0.2V(LB/UB controlled) 2.4 0.5 40 0.4 10 mA V V A VIN=Vss to Vcc CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc Cycle time=1s, 100%duty, IIO=0mA, CS0.2V, LB0.2V or/and UB0.2V, VIN0.2V or VINVCC-0.2V Test Conditions Min -1 -1 Typ1) Max 1 1 4 Unit A A mA
1. Typical values are measured at VCC=3.3V, TA=25C and not 100% tested.
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Revision 1.0 March 2002
K6F2016V4E Family
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load (See right): CL=100pF+1TTL CL=30pF+1TTL
CMOS SRAM
VTM3) R12)
CL1)
R22)
1. Including scope and jig capacitance 2. R1=3070, R2=3150 3. VTM =2.8V
AC CHARACTERISTICS(Vcc=3.0~3.6V, Industrial product:TA=-40 to 85C)
Speed Bins Parameter List Symbol Min Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output UB, LB Access Time Read Chip Select to Low-Z Output UB, LB Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output UB, LB Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write UB, LB Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z
1. The parameter is measured with 30pF test load.
55ns
1)
70ns Max 55 55 25 55 20 20 20 20 Min 70 10 10 5 0 0 0 10 70 60 0 60 60 50 0 0 30 0 5 Max 70 70 35 70 25 25 25 20 -
Units
tRC tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW
55 10 10 5 0 0 0 10 55 45 0 45 45 40 0 0 25 0 5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
DATA RETENTION CHARACTERISTICS
Item Vcc for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR Test Condition CSVcc-0.2V
1) 1)
Min 1.5 0 tRC
Typ2) 0.5 -
Max 3.6 2 -
Unit V A ns
Vcc= 1.5V, CSVcc-0.2V
See data retention waveform
1. 1) CSVcc-0.2V(CS controlled) or 2) LB=UBVcc-0.2V, CS0.2V(LB/UB controlled) 2. Typical values are measured at TA=25C and not 100% tested.
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K6F2016V4E Family
TIMING DIAGRAMS
CMOS SRAM
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)
tRC Address tOH Data Out Previous Data Valid tAA Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC Address tAA tCO tOH
CS
tHZ UB, LB tBA tBHZ OE tOLZ tBLZ tLZ Data Valid tOE tOHZ
Data out
High-Z
NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
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Revision 1.0 March 2002
K6F2016V4E Family
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
CMOS SRAM
tWC Address tCW(2) CS tAW tBW tWP(1) WE tAS(3) tDW Data in High-Z tWHZ Data out Data Undefined Data Valid tOW tDH High-Z tWR(4)
UB, LB
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS Controlled)
tWC Address tAS(3) CS tAW tBW UB, LB tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4)
Data out
High-Z
High-Z
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Revision 1.0 March 2002
K6F2016V4E Family
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC Address tCW(2) CS tAW tBW UB, LB tAS(3) tWP(1) WE tDW Data in Data Valid tDH tWR(4)
CMOS SRAM
Data out
NOTES (WRITE CYCLE)
High-Z
High-Z
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
DATA RETENTION WAVE FORM
CS or LB/UB controlled
VCC 3.0V tSDR Data Retention Mode tRDR
2.2V VDR CSVCC-0.2V or LB=UBVcc-0.2V CS or LB/UB GND
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Revision 1.0 March 2002
K6F2016V4E Family
PACKAGE DIMENSION
48 TAPE BALL GRID ARRAY(0.75mm ball pitch)
Top View Bottom View B B 6 A #A1 B C D 5 4 B1
CMOS SRAM
Unit: millimeters
3
2
1
C1 E C1/2 F G H B/2 Detail A A 0.35/Typ. Y 0.55/Typ. Notes. 1. Bump counts: 48(8 row x 6 column) 2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.) 3. All tolerence are 0.050 unless otherwise specified. 4. Typ: Typical 5. Y is coplanarity: 0.08(Max) -9-
Side View
D
C
Min A B B1 C C1 D E E1 E2 Y 5.90 6.90 0.40 0.80 0.30 -
Typ 0.75 6.00 3.75 7.00 5.25 0.45 0.90 0.55 0.35 -
Max 6.10 7.10 0.50 1.00 0.40 0.08
C
Revision 1.0 March 2002
C
E2
E1 E

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